ET1810, ET1811 | IP-ядро EtherCAT для ПЛИС Intel®

The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (Field Programmable Gate Array – i.e. a device containing programmable logical components). The EtherCAT functionality is freely configurable. The IP core can be combined with own FPGA designs, and it can be integrated in System-on-Chips (SoCs) with soft core processors or hard processor systems via the Avalon® or AMBA® AXI™ interfaces. The physical interfaces and internal functions, such as the number of FMMUs and SYNC managers, the size of the DPRAM, etc., are adjustable. The process data interface (PDI) and the distributed clocks are also configurable. The functions are compatible with the EtherCAT specification and the ET1100 EtherCAT ASIC.